RISC-V

ROAM_REFS: https://en.wikipedia.org/wiki/RISC-V

RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project began in 2010 at the University of California, Berkeley, transferred to the RISC-V Foundation in 2015, and on to RISC-V International, a Swiss non-profit entity, in November 2019. Like several other RISC ISAs, e.g. Amber (ARMv2) or OpenRISC, RISC-V is offered under royalty-free open-source licenses. The documents defining the RISC-V instruction set architecture (ISA) are offered under a Creative Commons license or a BSD License.

Mainline support for RISC-V was added to the Linux 5.17 kernel, in 2022, along with its toolchain. In July 2023, RISC-V, in its 64-bit variant called riscv64, was included as an official architecture of Linux distribution Debian, in its unstable version. The goal of this project was "to have Debian ready to install and run on systems implementing a variant of the RISC-V ISA." Gentoo also supports RISC-V. Fedora supports RISC-V as an alternative architecture as of 2025. The openSUSE Project added RISC-V support starting in 2018.

Some RISC-V International members, such as SiFive, Andes Technology, Synopsys, Alibaba's Damo Academy, Raspberry Pi, and Akeana, are offering or have announced commercial systems on a chip (SoCs) that incorporate one or more RISC-V compatible CPU cores.