MIPS

ROAM_REFS: https://en.wikipedia.org/wiki/MIPS_architecture

MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.

There are multiple versions of MIPS, including MIPS I, II, III, IV, and V, as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture.

The MIPS architecture has several optional extensions: MIPS-3D, a simple set of floating-point SIMD instructions dedicated to 3D computer graphics; MDMX (MaDMaX), a more extensive integer SIMD instruction set using 64-bit floating-point registers; MIPS16e, which adds compression to the instruction stream to reduce the memory programs require; and MIPS MT, which adds multithreading capability.

Computer architecture courses in universities and technical schools often study the MIPS architecture. The architecture greatly influenced later RISC architectures such as Alpha. In March 2021, MIPS announced that the development of the MIPS architecture had ended as the company is making the transition to RISC-V.

ROAM_REFS: https://en.wikipedia.org/wiki/Stanford_MIPS

MIPS, an acronym for Microprocessor without Interlocked Pipeline Stages, was a research project conducted by John L. Hennessy at Stanford University between 1981 and 1984. MIPS investigated a type of instruction set architecture (ISA) now called reduced instruction set computer (RISC), its implementation as a microprocessor with very large scale integration (VLSI) semiconductor technology, and the effective exploitation of RISC architectures with optimizing compilers. MIPS, together with the IBM 801 and Berkeley RISC, were the three research projects that pioneered and popularized RISC technology in the mid-1980s. In recognition of the impact MIPS made on computing, Hennessy was awarded the IEEE John von Neumann Medal in 2000 by the Institute of Electrical and Electronics Engineers (IEEE) (shared with David A. Patterson), the Eckert–Mauchly Award in 2001 by the Association for Computing Machinery, the Seymour Cray Computer Engineering Award in 2001 by the IEEE Computer Society, and, again with David Patterson, the Turing Award in 2017 by the ACM.

The project was initiated in 1981 in response to reports of similar projects at IBM (the 801) and the University of California, Berkeley (the RISC). MIPS was conducted by Hennessy and his graduate students until its conclusion in 1984. Hennessy founded MIPS Computer Systems in the same year to commercialize the technology developed by the project. In 1985, MIPS Computer Systems announced a new ISA, also called MIPS, and its first implementation, the R2000 microprocessor. The commercial MIPS ISA, and its implementations went on to be widely used, appearing in embedded computers, personal computers, workstations, servers, and supercomputers. As of May 2017, the commercial MIPS ISA is owned by Imagination Technologies, and is used mainly in embedded computers. In the late 1980s, a follow-up project called MIPS-X was conducted by Hennessy at Stanford.

The MIPS ISA was based on a 32-bit word. It supported 32-bit addressing, and was word-addressed. It was a load/store architecture—all references to memory used load and store instructions that copied data between the main memory and 32 general-purpose registers (GPRs). All other instructions, such as integer arithmetic, operated on the GPRs. It possessed a basic instruction set consisting of instructions for control flow, integer arithmetic, and logical operations. To minimize pipeline stalls, all instructions except for load and store had to be executed in one clock cycle. There were no instructions for integer multiplication or division, or operations for floating-point numbers. The architecture exposed all hazards caused by the five-stage pipeline with delay slots. The compiler scheduled instructions to avoid hazards resulting in incorrect computation whilst simultaneously ensuring that the generated code minimized execution time. MIPS instructions are 16 or 32 bit long. The decision to expose all hazards was motivated by the desire to maximize performance by minimizing critical paths, which interlock circuits lengthened. Instructions were packed into 32-bit instruction words (as MIPS is word-addressed). A 32-bit instruction word could contain two 16-bit operations. These were included to reduce the size of machine code. The MIPS microprocessor was implemented in NMOS logic.

ROAM_REFS: https://en.wikipedia.org/wiki/MIPS-X

MIPS-X is a reduced instruction set computer (RISC) microprocessor and instruction set architecture (ISA) developed as a follow-on project to the MIPS project at Stanford University by the same team that developed MIPS. The project was supported by the Defense Advanced Research Projects Agency (DARPA) and began in 1984. Its final form was described in a set of papers released in 1986–87. Unlike its older cousin, MIPS-X was never commercialized as a workstation central processing unit (CPU), and has mainly been seen in embedded system designs based on chips designed by Integrated Information Technology (IIT) for use in digital video applications.

MIPS-X, while designed by the same team and architecturally very similar, is instruction-set incompatible with the mainline MIPS architecture R-series processors. The MIPS-X processor introduced the concept of a delayed branch, which includes two delay slots. An MIPS-X processor also includes a Processor Status Word (PSW) register. The PSW register contains some flags that enable interruptions, overflow exceptions and other status information. The MIPS-X processor is obscure enough that, as of November 20, 2005, support for it is provided only by specialist developers (such as Green Hills Software), and is notably missing from the GNU Compiler Collection (GCC).

MIPS-X has become important among DVD player firmware hackers, since many DVD players (especially low-end devices) use chips based on the IIT design (and produced by ESS Technology), as their central processor. Devices such as the ESS VideoDrive system on a chip (SoC) also include a digital signal processor (DSP) (coprocessor) for decoding MPEG audio and video streams.