Power ISA

ROAM_REFS: https://en.wikipedia.org/wiki/Power_ISA

Power ISA is a reduced instruction set computer (RISC) instruction set architecture (ISA) currently developed by the OpenPOWER Foundation, led by IBM. It was originally developed by IBM and the now-defunct Power.org industry group. Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor.

Prior to version 3.0, the ISA is divided into several categories. Processors implement a set of these categories as required for their task. Different classes of processors are required to implement certain categories, for example a server-class processor includes the categories: Base, Server, Floating-Point, 64-Bit, etc. All processors implement the Base category.

Power ISA is a RISC load/store architecture. It has multiple sets of registers:

• 32 × 32-bit or 64-bit general-purpose registers (GPRs) for integer operations.
• 64 × 128-bit vector scalar registers (VSRs) for vector operations and floating-point operations.
  • 32 × 64-bit floating-point registers (FPRs) as part of the VSRs for floating-point operations.
  • 32 × 128-bit vector registers (VRs) as part of the VSRs for vector operations.
• 8 × 4-bit condition register fields (CRs) for comparison and control flow.
• 11 special registers of various sizes: Counter Register (CTR), link register (LR), time base (TBU, TBL), alternate time base (ATBU, ATBL), accumulator (ACC), status registers (XER, FPSCR, VSCR, SPEFSCR).

Instructions up to version 3.0 have a length of 32 bits, with the exception of the VLE (variable-length encoding) subset that provides for higher code density for low-end embedded applications, and version 3.1 which introduced prefixing to create 64-bit instructions. Most instructions are triadic, i.e. have two source operands and one destination. Single- and double-precision IEEE-754 compliant floating-point operations are supported, including additional fused multiply–add (FMA) and decimal floating-point instructions. There are provisions for single instruction, multiple data (SIMD) operations on integer and floating-point data on up to 16 elements in one instruction.

Power ISA has support for Harvard cache, i.e. split data and instruction caches, and support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. There is also support for both big and little-endian addressing with separate categories for moded and per-page endianness, and support for both 32-bit and 64-bit addressing.

Different modes of operation include user, supervisor and hypervisor.

ROAM_REFS: https://en.wikipedia.org/wiki/PowerPC

PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple--IBM--Motorola alliance, known as AIM. PowerPC, as an evolving instruction set, has been named Power ISA since 2006, while the old name lives on as a trademark for some implementations of Power Architecture–based processors.

Originally intended for personal computers, the architecture is well known for being used by Apple's desktop and laptop lines from 1994 until 2006, and in several videogame consoles including Microsoft's Xbox 360, Sony's PlayStation 3, and Nintendo's GameCube, Wii, and Wii U. PowerPC was also used for the Curiosity and Perseverance rovers on Mars and a variety of satellites. It has since become a niche architecture for personal computers, particularly with AmigaOS 4 implementations, but remains popular for embedded systems.

PowerPC was the cornerstone of AIM's PReP and Common Hardware Reference Platform (CHRP) initiatives in the 1990s. It is largely based on the earlier IBM POWER architecture, and retains a high level of compatibility with it; the architectures have remained close enough that the same programs and operating systems will run on both if some care is taken in preparation; newer chips in the Power series use the Power ISA.

ROAM_REFS: https://en.wikipedia.org/wiki/IBM_POWER_architecture

IBM POWER is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by IBM. The name is an acronym for Performance Optimization With Enhanced RISC.

The ISA is used as base for high end microprocessors from IBM during the 1990s and were used in many of IBM's servers, minicomputers, workstations, and supercomputers. These processors are called POWER1 (RIOS-1, RIOS.9, RSC, RAD6000) and POWER2 (POWER2, POWER2+ and P2SC).

The ISA evolved into the PowerPC instruction set architecture and was deprecated in 1998 when IBM introduced the POWER3 processor that was mainly a 32/64-bit PowerPC processor but included the IBM POWER architecture for backwards compatibility. The original IBM POWER architecture was then abandoned. PowerPC evolved into the third Power ISA in 2006.

[[https://upload.wikimedia.org/wikipedia/commons/thumb/3/3b/PowerISA-evolution.svg/220px-PowerISA-evolution.svg.png]]

IBM continues to develop PowerPC microprocessor cores for use in their application-specific integrated circuit (ASIC) offerings. Many high volume applications embed PowerPC cores.

ROAM_REFS: https://openpower.foundation/

• OpenPOWER Foundation

Open Developer Community for the POWER Architecture

“The Most Open and High-Performance Processor Architecture and Ecosystem in the Industry”

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