(www.st.com) STM32 Microcontrollers (MCUs) - STMicroelectronics

ROAM_REFS: https://www.st.com/en/microcontrollers-microprocessors/stm32h733vg.html

* Description

STM32H733xG devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 550 MHz. The Cortex® -M7 core features a floating-point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. The Cortex -M7 core includes 32 Kbytes of instruction cache and 32 Kbytes of data cache. STM32H733xG devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.

STM32H733xG devices incorporate high-speed embedded memories with 1 Mbyte of flash memory, up to 564 Kbytes of RAM (including 192 Kbytes that can be shared between ITCM and AXI, plus 64 Kbytes exclusively ITCM, plus 128 Kbytes exclusively AXI, 128 Kbyte DTCM, 48 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multilayer AXI interconnect supporting internal and external memory access. To improve application robustness, all memories feature error code correction (one error correction, two error detections).

The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC coprocessor for trigonometric functions and FMAC unit for filter functions). All the devices offer three ADCs, two DACs, two operational amplifiers, two ultra-low-power comparators, a low-power RTC, four general-purpose 32-bit timers, 12 general-purpose 16-bit timers including two PWM timers for motor control, five low-power timers, a true random number generator (RNG), and a cryptographic acceleration cell, and a HASH processor. The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces.

* All features

• Includes ST state-of-the-art patented technology
• Core
  • 32-bit Arm® Cortex®-M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction cache allowing 0-wait state execution from embedded flash memory and external memories, frequency up to 550 MHz, MPU, 1177 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
  • 1 Mbyte of embedded flash memory with ECC
  • SRAM: total 564 Kbytes all with ECC, including 128 Kbytes of data TCM RAM for critical real-time data + 432 Kbytes of system RAM (up to 256 Kbytes can remap on instruction TCM RAM for critical real time instructions) + 4 Kbytes of backup SRAM (available in the lowest-power modes)
  • Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
  • 2 x Octo-SPI interface with XiP and on-the-fly decryption support
  • 2 x SD/SDIO/MMC interface
  • Bootloader with security services support (SFI and SB-SFU)
• Graphics
  • Chrom-ART Accelerator graphical hardware accelerator enabling enhanced graphical user interface to reduce CPU load
  • LCD-TFT controller supporting up to XGA resolution
• Clock, reset and supply management
  • 1.62 V to 3.6 V application supply and I/O
  • POR, PDR, PVD and BOR
  • Dedicated USB power
  • Embedded LDO regulator
  • Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
  • External oscillators: 4-50 MHz HSE, 32.768 kHz LSE
• Low power
  • Sleep, Stop and Standby modes
  • V_BAT supply for RTC, 32×32-bit backup registers
• Analog
  • 2×16-bit ADC, up to 3.6 MSPS in 16-bit: up to 18 channels and 7.2 MSPS in double-interleaved mode
  • 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12 channels
  • 2 x comparators
  • 2 x operational amplifier GBW = 8 MHz
  • 2× 12-bit D/A converters
• Digital filters for sigma delta modulator (DFSDM)
  • 8 channels/4 filters
• 4 DMA controllers to offload the CPU
  • 1 × MDMA with linked list support
  • 2 × dual-port DMAs with FIFO
  • 1 × basic DMA with request router capabilities
• 24 timers
  • Seventeen 16-bit (including 5 x low power 16-bit timer available in stop mode) and four 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
  • 2x watchdogs, 1x SysTick timer
• Debug mode
  • SWD and JTAG interfaces
  • 2-Kbyte embedded trace buffer
• Up to 114 I/O ports with interrupt capability
• Up to 35 communication interfaces
  • Up to 5 × I2C FM+ interfaces (SMBus/PMBus™)
  • Up to 5 USARTs/5 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1 x LPUART
  • Up to 6 SPIs with 4 with muxed duplex I2S for audio class accuracy via internal audio PLL or external clock and up to 5 x SPI (from 5 x USART when configured in synchronous mode)
  • 2x SAI (serial audio interface)
  • 1× FD/TT-CAN and 2x FD-CAN
  • 8- to 14-bit camera interface
  • 16-bit parallel slave synchronous interface
  • SPDIF-IN interface
  • HDMI-CEC
  • Ethernet MAC interface with DMA controller
  • USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip FS PHY and ULPI for external HS PHY
  • SWPMI single-wire protocol master I/F
  • MDIO slave interface
• Mathematical acceleration
  • CORDIC for trigonometric functions acceleration
  • FMAC: Filter mathematical accelerator
• Digital temperature sensor
• Cryptographic/HASH acceleration
  • AES 128, 192, 256, TDES, HASH (MD5, SHA-1, SHA-2), HMAC
  • 2x OTFDEC AES-128 in CTR mode for Octo-SPI memory encryption/decryption
• True random number generator
• CRC calculation unit
• RTC with subsecond accuracy and hardware calendar
• ROP, PC-ROP, tamper detection, secure firmware upgrade support
• 96-bit unique ID
• All packages are ECOPACK2 compliant

ROAM_REFS: https://www.st.com/en/microcontrollers-microprocessors/stm32l432kc.html

* Description

The STM32L432xx devices are the ultra-low-power microcontrollers based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.

The STM32L432xx devices embed high-speed memories (Flash memory up to 256 Kbyte, 64 Kbyte of SRAM), a Quad SPI flash memories interface and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

The STM32L432xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall.

The devices offer a fast 12-bit ADC (5 Msps), two comparators, one operational amplifier, two DAC channels, a low-power RTC, one general-purpose 32-bit timer, one 16-bit PWM timer dedicated to motor control, four general-purpose 16-bit timers, and two 16-bit low-power timers.

In addition, up to 3 capacitive sensing channels are available.

They also feature standard and advanced communication interfaces.

The STM32L432xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C (+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.

Some independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMP and comparators

The STM32L432xx family offers a single 32-pin package.

* All features

• Ultra-low-power with FlexPowerControl
  • 1.71 V to 3.6 V power supply
  • -40 °C to 85/105/125 °C temperature range
  • 8 nA Shutdown mode (2 wakeup pins)
  • 28 nA Standby mode (2 wakeup pins)
  • 280 nA Standby mode with RTC
  • 1.0 μA Stop 2 mode, 1.28 μA with RTC
  • 84 μA/MHz run mode
  • Batch acquisition mode (BAM)
  • 4 μs wakeup from Stop mode
  • Brown out reset (BOR)
  • Interconnect matrix
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions
• Performance benchmark
  • 1.25 DMIPS/MHz (Drystone 2.1)
  • 273.55 CoreMark® (3.42 CoreMark/MHz @ 80 MHz)
• Energy benchmark
  • 176.7 ULPBench® score
• Clock Sources
  • 32 kHz crystal oscillator for RTC (LSE)
  • Internal 16 MHz factory-trimmed RC (±1%)
  • Internal low-power 32 kHz RC (±5%)
  • Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy)
  • Internal 48 MHz with clock recovery
  • 2 PLLs for system clock, USB, audio, ADC
• Up to 26 fast I/Os, most 5 V-tolerant
• RTC with HW calendar, alarms and calibration
• Up to 3 capacitive sensing channels
• 11x timers: 1x 16-bit advanced motor-control, 1x 32-bit and 2x 16-bit general purpose, 2x 16-bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer
• Memories
  • Up to 256 KB single bank Flash, proprietary code readout protection
  • 64 KB of SRAM including 16 KB with hardware parity check
  • Quad SPI memory interface
• Rich analog peripherals (independent supply)
  • 1x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 μA/Msps
  • 2x 12-bit DAC output channels, low-power sample and hold
  • 1x operational amplifier with built-in PGA
  • 2x ultra-low-power comparators
• 14x communication interfaces
  • USB 2.0 full-speed crystal less solution with LPM and BCD
  • 1x SAI (serial audio interface)
  • 2x I2C FM+(1 Mbit/s), SMBus/PMBus
  • 3x USARTs (ISO 7816, LIN, IrDA, modem)
  • 1x LPUART (Stop 2 wake-up)
  • 2x SPIs (and 1x Quad SPI)
  • CAN (2.0B Active)
  • SWPMI single wire protocol master I/F
  • IRTIM (Infrared interface)
• 14-channel DMA controller
• True random number generator
• CRC calculation unit, 96-bit unique ID
• Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™
• All packages are ECOPACK2® compliant